The present invention relates generally to a monitoring circuit for a vehicle module. More particularly, the invention relates to a monitoring circuit for a vehicle module interfacing with an open collector circuit residing within a different module than the module containing the monitoring circuit, wherein there is a significant ground voltage offset between the monitoring circuit and the open collector circuit.
A large digital signal system typically includes a plurality of modules which communicate with other modules by transmitting data over a shared signal line. In general, most of these modules interface with at least two other modules which may or may not be under the same limitations and constraints. For example, two different modules residing within a given digital system may be connected to different power supplies and different ground potentials. Such differences in limitations and constraints of two or more different modules may introduce miscommunication between various digital signal modules and may cause erroneous results in a digital signal system. One system which may experience such a difference is a transmitting module having an open collector output circuit and a receiving module having a monitoring circuit. The monitoring circuit of the receiving module interfaces with the open collector output circuit of the transmitting module, and receives an input signal therefrom. These two circuits are described below in greater detail.
FIG. 1 illustrates a typical open collector output circuit 10 contained within a transmitting module of a vehicle. The open collector output circuit 10 includes an input resistor (Rb) 12, a first bipolar junction transistor (BJT) 14, a second BJT 16 and a current limiting resistor (Re) 18. Each of the first and second BJTs 14 and 16, respectively, includes a base junction 28 or 34, an emitter junction 30 or 36, and a collector junction 26 or 32. The base junction 28 of the first BJT 14 is connected to the input resistor (Rb) 12, which transmits an input signal received via the input port 22 from its adjacent circuit. The collector junction 26 of the first BJT 14 provides an output of the open collector output circuit 10 to its adjacent circuit, or a monitoring circuit 50 (FIG. 2) in the present invention. The emitter junction 30 of the first BJT 14 is connected to ground 24 through the current limiting resistor (Re) 18.
The base junction 34 of the second BJT 16 is connected to the emitter junction 30 of the first BJT 14 and the current limiting resistor 18. The collector junction 32 of the second BJT 16 is connected to the input resistor 12 and the emitter junction 36 of the second BJT 16 is connected to a ground 24 of the transmitting module. The current limiting resistor (Re) 18 provides a base-emitter voltage for the second BJT 16 and a voltage offset to the collector of the first BJT 20. In turn, the second BJT 16 provides overcurrent shutdown by shunting the base current of BJT 14.
The open collector output circuit 10 typically interfaces with a monitoring circuit 50 illustrated in FIG. 2. The monitoring circuit 50 includes a first capacitor (C1) 54, which is connected in parallel to the monitoring circuit 50 and receives an input signal from an input port 52. The other end of the first capacitor (C1) 54 is also connected to a RF ground 56. The monitoring circuit 50 also includes an isolation diode 58 connected in series to the monitoring circuit 50. Via the isolation diode 58, a first resistor 60 is connected in series to the input port 52, and receives the input signal therefrom. The first resistor 60 is connected to a second resistor 62 and a second capacitor(C2) 66 at node A. A first BJT 70 of the monitoring circuit 50 is also connected at node A to the first and second resistors 60 and 62, respectively, and to the second capacitor (C2) 66. The other ends of the second resistor 62 and the second capacitor (C2) 66 are connected to a DC voltage supply, VDD, and a receiver ground 68, respectively.
The first BJT 70 of the monitoring circuit 50 includes a base junction 86, an emitter junction 84, and a collector junction 88. The base junction 86 of the first BJT 70 is connected to node A. The emitter junction 84 of the first BJT 70 is connected to a third resistor 72 which, in turn, is connected to the voltage supply, VDD. The collector junction 88 of the first BJT 70 is connected to a fourth resistor 74, which is then connected to a second BJT 78 and a fifth resistor 76 at node B. The first BJT 70 provides base drive for the second BJT 78. The other end of the fifth resistor 76 is grounded.
Similarly, the second BJT 78 also includes a base junction 92, an emitter junction 94, and a collector junction 90. The base junction 92 of the second BJT 78 is connected to the first BJT 70 via the fourth resistor 74, and derives base current therefrom. The emitter junction 94 of the second BJT 78 is connected to receiver ground 68. The collector junction 90 of the second BJT 78 is connected to a power supply, VDD, through a sixth resistor 80. The collector junction 90 of the second BJT 78 operates as an output port of the monitoring circuit 50 and provides output signals to its adjacent CMOS transistor input (not shown). The output signal from the output port 82 of the monitoring circuit 50, (or the CMOS INPUT) has a logical one value of less than 0.2xc3x97VDD volt for a logic low level and greater than 0.7xc3x97VDD volts as a logic high.
When the input signal received from the open collector output circuit 10 is high, there is no current flow through the isolation diode 58 and provides no base current for the first BJT 70 of the monitoring circuit 50. When the first BJT 70 is turned off, the second BJT 78 also gets turned off because there is no base current supplied to the second BJT 78. As will be apparent to one skilled in the art, the second BJT 78, when turned off, induces the monitoring circuit 50 to provide an output signal that is high, or at a logical one, due to the pull-up voltage through the sixth resistor 80.
Contrary to this, when the input signal received from the open collector output circuit 10 is low, or at a logical zero, the current flows from the power supply, VDD, via the second and first resistors 62 and 60, respectively, to the isolation diode 58. The current turns on the first BJT 70, and causes the current to flow from the emitter junction 84 of the first BJT 70 to the collector junction 88 of the first BJT 70. This current flow through the collector junction 88 of the first BJT 70 provides base current for the second BJT 78, which then turns on in a saturation mode. Appropriate values for the third resistor 74 and the input current are selected to minimize the time the second BJT 78 stays in a linear mode. When the second BJT 78 turns on, the monitoring circuit 50 produces an output signal which is low, or at a logical zero. As a result, the current flows from the collector junction 90 of the second BJT 78 to the emitter junction 94 of the second BJT 78.
The monitoring circuit 50 is generally contained within a different module than the module containing the open collector output circuit 10. Thus, there may exist a significant ground differential between the two circuits. The ground differential, together with the increased emitter voltage of the first BJT 14 of the open collector output circuit 10 due to the second BJT 16 as described above, causes the voltage of the open collector output circuit 10 to be in a range of 1-3.5 V (0.2 Vddxe2x88x920.7 Vdd) as seen by the monitoring circuit 50.
To be effective, the monitoring circuit 50 must operate in a saturated mode. For the monitoring circuit 50 to operate in a saturated mode, the monitoring circuit 50 must have a predetermined amount of base current supplied to the second BJT 78 from the collector junction 88 of the first BJT 70. Thus, the emitter current must be large enough for the monitoring circuit 50 to operate in a saturated mode within a predetermined period. However, more of the emitter current and/or time is required for the monitoring circuit to operate in a saturated mode due to the ground differential between the monitoring circuit and the open collector output circuit. When the specified amount of emitter current of the first BJT 70 is not supplied within the given period, this ground differential may cause signal noises that induce false signaling, or false edges, at the output 82 of the monitoring circuit 50.
Additionally, the monitoring circuit 50 illustrated in FIG. 2 has poor noise immunity and fails to provide hysteresis. More specifically, the noise causes the monitoring circuit 50 to function as an amplifier rather than a switch when the resistance of the third resistor 72 is above a predetermined threshold. The noise occurring through the single switching point will cause multiple pulses and false signaling at the output 82 of the monitoring circuit 50. Furthermore, the longer the monitoring circuit 50 takes to operate in a non-saturated mode, the more the noise can occur and cause miscommunication.
What is needed is a monitoring circuit that minimizes time when the monitoring circuit is in a linear mode, and reduces noise occurring during the transfer of data signals. Accordingly, it is an object of the present invention to provide a monitoring circuit that maximizes a turn-on rate of a digital circuit receiving an input from the monitoring circuit. It is also an object of the present invention to provide such a monitoring circuit that can be manufactured cost efficiently.
In accordance with the teachings of the present invention, a monitoring circuit interfacing an open collector output circuit with a voltage offset is provided. Conventionally, the voltage offset exhibited between the monitoring circuit and the open collector output circuit prevented direct interfacing of the monitoring circuit with a digital input of an adjacent digital circuit. In order to solve the above mentioned problem, the monitoring circuit of the present invention includes a first bipolar junction transistor (BJT) connected to an open collector output circuit having a first ground. The monitoring circuit has a second ground that is at a different location than the first ground. The first and second grounds create an appreciable voltage offset therebetween when the monitoring circuit interfaces with the open collector output circuit. The monitoring circuit also includes a second BJT connected to the first BJT in a loop configuration so that at least one of the first and second BJTs increases base current drive to its respective BJT. The monitoring circuit of the present invention therefore maximizes a turn-on rate of its adjacent digital circuit.